In the field of semiconductor fabrication, the use of dielectric materials having a low dielectric constant, known as low-K materials, is well known. Low-K dielectrics are used primarily in backend processing. Backend processing refers generally to processing subsequent to the formation of transistors in the wafer substrate to interconnect the transistors, typically with multiple levels of interconnect. Each interconnect level is separated by an interlevel dielectric (ILD). The individual interconnects within a single interconnect level are also separated by a dielectric material that may or may not be the same as the ILD. Vias or contacts are formed in the ILD's and filled with conductive material to connect the interconnect levels in a desired pattern to achieve a desired functionality.
The spacing between adjacent interconnects within an interconnect level and the spacing between vertically adjacent levels have both decreased as device complexity and performance have increased. Minimizing cross coupling between the many signals within a device is now a significant design consideration. The primary source of signal cross coupling or cross talk is capacitive. A pair of adjacent interconnects, whether within a single interconnect level or in vertically adjacent interconnect levels, separated by an intermediate dielectric material form an unintended parallel plate capacitor. Minimizing cross coupling requires a minimization of the capacitance between any pair of adjacent interconnects, especially those interconnects that carry signals that switch a high frequency.
One popular approach to minimizing cross talk includes the use of low-K dielectric materials as the ILD. Low-K materials reduce cross talk because the capacitance of a parallel plate capacitor is directly proportional to the dielectric constant of the material between the capacitor plates. A lower dielectric constant material translates into a lower capacitance and a lower cross coupling.
Various low-K materials have been used in low-K backend processing with mixed results. Integration of low-K material into existing fabrication processes is particularly challenging in the case of backend processing that includes the use of chemical-mechanical polishing (CMP). CMP is a technique by which each interconnect level is formed in many existing processes. In a CMP process, as implied by its name, a film or layer is physically polished with a rotating polishing pad in the presence of a “slurry” that contains mechanical abrasion components and/or chemical components to produce a smooth upper surface and to remove excess conductive material and thereby isolate the individual interconnects from one another.
Low-K materials are generally not easily integrated into a CMP-based backend process. Conductive materials and Low-K materials tend to exhibit dishing and erosion and other forms of deterioration under chemical mechanical polishing and are susceptible to the polishing pressure and polishing time. To combat this problem, capping materials have been formed over the low-K dielectrics to act as a CMP stop. Unfortunately, adhesion between many materials used as low-K materials and other materials suitable for use as a CMP stopping layer is often not good. In addition, the capping materials with higher dielectric constants degrade the capacitive performance of the low-K materials. It would be desirable, therefore, to implement a process integrating low-K ILD's into a CMP backend process flow.
Thus, a need still remains for an integrated circuit processing system that integrates a low-K dielectric with a CMP process that doesn't weaken or damage the low-K ILD. In view of the demand for smaller integrated circuit geometries and the increasing operational frequencies of the end devices, it is increasingly critical that answers be found to these problems. Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.